Startup Substrate is building next-generation semiconductor fabs using advanced X-ray lithography. This goes beyond extreme ...

Concept of mask/wafer co-optimization by moving the shot with mask and wafer double simulation to minimize wafer error. VSB shot configurations and its corresponding ...

Imec has achieved the first successful wafer-scale fabrication of solid-state nanopores using EUV lithography on 300mm wafers. This innovation transforms nanopore technology from a lab-scale concept ...

Precision alignment in semiconductor lithography demands nanometer-scale accuracy, as even minor misalignments between the mask and wafer can ...

Intel has announced a new deal with ASML, the semiconductor manufacturing equipment firm, aimed at boosting research into cutting-edge construction techniques. Share on Facebook (opens in a new window ...

This is the second blog in a three-part series on pixel-level dose correction (PLDC). The first installment was “Improving Uniformity and Linearity for All Masks” from January 29, 2025. PLDC: A new ...

One of the main challenges in developing semiconductor chip technology is making electronic components smaller and more effective. This difficulty is most noticeable in lithography, which is the ...

ASML Holding ASML, a leading manufacturer of semiconductor lithography tools, is at the center of a major shift in advanced ...

Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly ...