Adder and Subtractor Verilog Code with Test Bench

HAVEN: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

This repository accompanies the paper "HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers", accepted at DATE 2025. HaVen is a novel framework designed to enhance ...

GitHub

GURUNANDINIDEVI/100-Days-Verilog-Coding

👩‍💻 Connect With Me If you’re passionate about VLSI, RTL Design, or Verilog, feel free to connect and collaborate!

Some results have been hidden because they may be inaccessible to you

Show inaccessible results

HAVEN: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

GURUNANDINIDEVI/100-Days-Verilog-Coding

Trending now