IEEE

Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Device Contacts

Abstract: A device architecture with n-MOS and p-MOS transistors stacked on top of each other is considered a key option to continue scaling in the semiconductor industry. We report experimental ...
IEEE

3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling

Abstract: We demonstrate 3-D self-aligned stacked NMOS-on-PMOS multiple Si nanoribbon transistors with successful integration of vertically stacked dual source/drain EPI process and vertically stacked ...